In packet-based communication systems, an initiator sends a read-request packet to a target device. The target sends back a response data packet after some time. For the effective transmission of packets, the device should be able to send many read-request packets before receiving response packets from the target. To support this, the initiator assigns a token/tag to each read-request packet. The initiator can thus identify and handle response packets. The target should use the same token/tag in a response packet. The token is freed up and can be reused once this two-way transaction is completed. For each outstanding token, the initiator needs to remember properties such as address, data length, etc., of the read-request-packet, until a response packet is received.
At the start of a session all tokens are available and can be issued in any order. Once all the tokens are consumed, however, a new read-request packet can be formed only after a response packet is received to release the associated token. This situation occurs also in other applications of storage elements beyond packet-based communication systems.
A communications system will typically have 1024 or more tokens, and against each token, information about the read-request packet is stored (e.g. a 32 bit address, 12 bit data length, etc.). A circuit designer is thus forced to make use of SRAM/register-arrays instead of flip-flops to store this information and to save on chip area.
FIG. 1 shows a memory 10 that stores a set of token information 12, addressed as 0000 to 1023. The Most Significant Bit (MSB) 14 is used to indicate token status; a logic ‘1’ indicates token is in use and a logic ‘0’ indicates a token is free. Token information is output by the read port 22 to generate a respective token 24. To generate a new token, a memory controller firstly needs to check the status bit to determine whether the token address is already in use or not.
When memory is implemented in SRAM a problem that arises is the initial (power on) values of the SRAM locations cannot be predicted. A discrete “zeroing task” of the memory addresses thus required upon power-on, or soft reset, so that token assignment can occur in a sequential manner.
Since only one location can be accessed at a time, in this example, initialization requires 1024 clock cycles. As the size of the array increases, the time needed to initialize the RAM will increase, requiring the other parts of the related system to wait until the initialization completes. This can cause considerable performance degradation.
FIG. 2 shows a further implementation, in which an address generator (binary counter) 30 is used to access all locations of the RAM 10 during initialization. By counting through the set of addresses via the write address port 18, all status bit locations 14 are initialized with known value of logic “0” via the write port 20.
Once the address counter reaches address no. 1023, an overflow condition is generated, and an RS flip-flop 32 causes a logical multiplexer 34 to connect a token generator 36 to the write address port 18.